Foundry: One-sentence take
All roads point to this: N2 economics + CoWoS capacity + power/cooling. Prices are rising, packaging stays tight even as it expands, and policy keeps nudging capacity out of China. If you don’t model power and cooling, your N2 model is half a model.
1) September highlights that actually moved the needle
- TSMC’s AI design alliance with Ansys, Cadence, and Synopsys shifts PPA optimization earlier in the flow. The practical read-through is lower data-center TCO for N3/N2 customers (mid-refs below).
- N2 price signals firmed: industry chatter coalesced around $30k+ per wafer for 2nm and a 5–10% price lift for advanced nodes in 2026. That forces BOM re-plans and pushes second-sourcing conversations.
- Samsung Foundry reportedly floated lower N2 pricing (rumor/briefings). Without yield and reliability, price alone won’t convert marquee wins—but it does open doors.
- SK hynix announced HBM4 readiness and High-NA EUV adoption, strengthening the memory-logic co-optimization story and pulling CoWoS-L demand forward.
- US policy tightened: partial revocation of China-bound equipment approvals for KR memory fabs raises the bar for upgrades in China and accelerates re-location to KR/US/TW/JP.
- CoWoS capacity keeps climbing—roughly ~75k wpm in 2025 → ~90–100k wpm in 2026—yet remains functionally scarce for large-die AI parts.
Mid-sources: Reuters on TSMC’s AI power-saving alliance; SEMI’s Q2 equipment billings (+24% YoY); CHIPS/NIST updates on US fab incentives (full links at the end).
2) Who goes N2 when: Apple · MediaTek · NVIDIA
This is where pricing meets reality—customer timing and packaging slots.
| Customer | Earliest concrete signal | Commercial window (est.) | Product focus | What to watch |
|---|---|---|---|---|
| Apple | Repeatedly cited among earliest N2 anchor customers | 2026 for select mobile/M-class variants | Mobile SoC, notebook/HPC derivatives | BOM pressure from $30k+ wafers; competition for CoWoS slots where needed |
| MediaTek | Publicly stated N2 tape-out (Sep 2025) | 2026 flagship AP first | Flagship AP; NB/auto options later | Origin-of-manufacture asks; alignment with US/JPN capacity |
| NVIDIA | N2P/N2X under evaluation (no public commit) | 2027+ candidate | AI/HPC ASIC + HBM4 | Packaging first: CoWoS-L/WMCM, plus Optical I/O roadmap pacing |
Read-through: Apple/MediaTek’s earlier N2 entry magnifies wafer-price pressure and packaging slot competition. NVIDIA’s gating factor is still packaging + I/O, not the front-end node per se; any N2 move likely rides alongside HBM4 + CoWoS-L/WMCM + Optical I/O.
3) Pricing & supply: where the bottleneck really sits
- N2 pricing: Market talk now centers on $30k+ for N2 wafers and a 5–10% advanced-node lift in 2026. The directional takeaway matters more than any single sticker price—volume, options, and service level move the final number.
- CoWoS capacity: 2025 roughly ~65–75k wpm, stepping up toward ~90–100k wpm in 2026. Still tight for giant AI dies and many-high HBM stacks. Expect sticky packaging lead times and firm pricing as long as AI demand remains front-loaded.
Mid-sources: Trendforce/industry trackers for CoWoS; SEMI for equipment billings; Reuters on TSMC pricing/alliances (links consolidated below).
4) CAPEX that matters: substrates & tools
N2 + HBM4 era advantages increasingly accrue downstream.
| Segment | Key players | 2025–26 CAPEX direction | Why it matters |
|---|---|---|---|
| ABF / Si interposer substrates | Ibiden, Unimicron, Shinko, AT&S | +20–40% YoY style expansions | Larger panels, laser/drilling, plating: essential for CoWoS-L and high-stack HBM |
| Back-end/packaging tools | ASML (High-NA), TEL, Disco, AMAT, Lam, KLA | EUV + etch + back-end lines expanding | CoWoS-L/WMCM ramp; metrology/laser capacity becomes a hard gate |
Bottom line: In this cycle, substrate & back-end CAPEX can out-grow front-end, because that’s where the AI bottleneck sits.
5) Power & cooling: the TCO hinge (Immersion · BPD · Optical I/O)
- Immersion cooling is moving from “pilot” to default for new AI halls. With kW-class per rack density, air alone breaks. NVIDIA/OpenAI hyperscale plans essentially assume liquid.
- Backside Power Delivery (BPD) on N2 (TSMC/Intel) separates power/signal planes, improving IR drop/efficiency and raising routing freedom—especially helpful for chiplets.
- Optical I/O shifts the performance ceiling: Pair CoWoS-L/WMCM + Optical I/O and you relieve bandwidth + thermals at once. Several roadmaps point to 2026–27 for visible traction.
If you only model nodes, you’ll miss the PUE math. Real TCO = node + packaging + cooling/power infrastructure.
6) Kori’s Notes
- Price ≠ moat. Without yield, reliability, and slot certainty, price moves end up temporary.
- The bottleneck migrates, it doesn’t vanish: CoWoS-S → L → WMCM. Follow the CAPEX into substrates, lasers, and metrology.
- For portfolio or vendor strategy, watch three dials each quarter:
- N2 tape-in/out cadence by customer class (mobile vs. HPC),
- Packaged throughput & wait times (CoWoS-L/WMCM),
- Cooling adoption (immersion) + BPD/Optical I/O milestones.
- Policy is a structural tailwind for KR/US/TW/JP footprints; treat China upgrades as scenario, not baseline.
Mid-article references
- Reuters on TSMC + EDA AI power-saving alliance (Sep 25, 2025)
- SEMI on Q2’25 global equipment billings (+24% YoY)
(Full reference list with links is consolidated below.)
Consolidated references
- SEMI — Global Semiconductor Equipment Billings Increased 24% YoY in Q2 2025
- Reuters — TSMC and EDA firms tap AI to help chips use less energy (2025-09-25)
- Samsung Electronics Analysis｜HBM3E , 2nm, Texas Fab
- International Monetary Fund | IMF
(Optional background you can add when needed: CHIPS/NIST GlobalFoundries program page; Trendforce/industry trackers for CoWoS capacity.)
Q&A
Q1. When will 2nm be felt by end-users, not just on slides?
A. 2nm first lands where PPA per watt buys back data-center cost—HPC/ASIC before mass mobile. Real user-level impact clusters around 2026–2027, as supply/yield improve and packaging lead times ease.
Q2. Will CoWoS bottlenecks clear in 2026?
A. They ease, not disappear. With CoWoS-L/WMCM ramping and HBM stacks growing taller, congestion shifts spots. Plan for tight but improving lead times through 2026.
Q3. How do US restrictions on China fabs change the map?
A. Upgrades in China get harder, nudging CAPEX toward KR/US/TW/JP and reinforcing “friend-shoring.” For memory + HBM packaging, expect non-China chains to keep gaining weight.
#Foundry #2nm #CoWoS #HBM4 #N2Roadmap #CAPEX #ImmersionCooling #BPD #OpticalIO #TSMC #SamsungFoundry #NVIDIA #MediaTek #Apple #Semiconductor
